Frequency synthesizers are utilized for example in radio systems in which a radio frequency (RF) signal having properties defined by system specifications is always present. Quite often, a phase locked loop (PLL) is used to generate the RF signal. PLL is used to tune the RF signal into pre-defined system frequencies, and it is a very accurate solution for frequency synthesis.
FIG. 1 illustrates a simplified block diagram of PLL. Key components of PLL often include a voltage-controlled oscillator (VCO) 100, a phase/frequency detector 104 and division logic 102. VCO 100 provides an output RF signal, which is tuned by inputs received from the phase/frequency detector 104. The output signal of the VCO 100 is directed to the phase/frequency detector 104 through the division logic 102 which divides the RF signal into a lower frequency to enable the phase/frequency detector 104 to compare the output signal of the VCO 100 with a reference signal. The reference signal is typically provided by an accurate oscillator, for example a crystal oscillator, which oscillates on a frequency lower than that of the RF signal. The phase/frequency detector 104 compares the input signal received through the division logic 102 with the reference signal and tunes the VCO 100 accordingly. The purpose of the phase/frequency detector 104 is to tune the VCO 100 such that the phase/frequency of the input signals of the phase/frequency detector 104 remain as close to one another as possible.
The VCO 100 may provide its output signal with different phase shifts, and these output signals with different phases may be applied to a multiplexer provided between the VCO 100 and the frequency divider 102. FIG. 2 illustrates a simplified block diagram of such multiplexer 208. Quadrature input signals SIN I and SIN Q having a 90-degree phase difference are converted to square wave signals S1 and S2 in converters 202 and 204, respectively, and then input to an asynchronous multiplexer 208. As a result, signals S1 and S2 have a phase shift of ¼ of a period of the signals. The asynchronous multiplexer selects one of the signals as an output signal OUT under control of a selection control signal SEL. The signals S1, S2, and SEL are illustrated in FIG. 3A, and the output signal OUT is illustrated in FIG. 3B. In FIG. 3A, S1 is illustrated by a solid line, S2 by a dashed line, and SEL by a dotted line. At first, the asynchronous multiplexer 208 controlled by the selection control signal SEL selects signal S1 as the output signal OUT. After the point when selection control signal level changes from high to low, the multiplexer 208 selects signal S2 as the output signal OUT. FIG. 3B illustrates the result. At a moment just before the state of the selection control signal SEL changed, the level of signal S1 changed from low to high. The state of signal is low at the same moment. As can be seen in FIG. 3B, this causes a glitch to the output signal at time instant T1. The glitch may cause undesired effects in the components following the multiplexer 208 and generate spurious RF signals.